The present invention relates to a charge detecting device, and more particularly to a solid state imaging element and a solid state imaging device using a CMOS image sensor of a low noise amplification type which can implement a high picture quality, and a charge detecting device requiring signal charge detection having high precision which is to be used in a comparator or the like for an analog digital converter (ADC).
As the solid state imaging element, conventionally, a function of amplifying a charge signal photoelectrically converted in a pixel has been provided. Consequently, the invention for enhancing the characteristic of the image sensor has been made and put into practical use.
As a pixel having the function of amplifying the photoelectrically converted signal, thus, there has been proposed a method of providing, on a pixel, a signal amplifying circuit constituted by an MOS type field effect transistor as is disclosed in IEEE Journal of Solid-State Circuits, vol. SC-4, No. 6 (1969) “Photosensitivity and Scanning of Silicon Image Detector Arrays” and Jpn. Pat. Appln. KOKAI Publication No. 50-134393.
An MOS image sensor in which a pixel is constituted by an MOS type field effect transistor can be manufactured in a process almost similar to that of a general-purpose CMOS. Therefore, the manufacture can easily be carried out and a simple power source can be used because an ordinary CMOS clock is enough for a driving pulse and an operation can be performed with a single power source. In addition, it is easy to integrate a CMOS digital circuit and an analog circuit in the same chip.
Such an MOS image sensor has some excellent features as compared with a CCD image sensor, for example, an image sensor having a multifunction can be constituted. In recent years, consequently, attention has been mainly paid to the MOS image sensor as an image sensor to be incorporated in a portable imaging device which requires low power consumption and a reduction in a size.
FIG. 5 shows a conventional amplification type pixel constituted by the MOS type field effect transistor.
First of all, an amplification type pixel constituted by the conventional MOS type field effect transistor will be described with reference to FIG. 5.
FIG. 5 illustrates the structure of a unit pixel by using an equivalent circuit.
In FIG. 5, the reference numeral 10-1 denotes a photodiode for generating an electric charge through irradiated light.
Moreover, the reference numeral 10-2 denotes an MOS type field effect transistor for reset which serves to connect an N side electrode 10-3 of the photodiode 10-2 to a voltage wiring 10-4 of a reset voltage (source) VRS.
Furthermore, the reference numeral 10-5 denotes an MOS type field effect transistor for amplification which has a gate electrode connected to the N side electrode 10-3 of the photodiode 10-1 and a drain electrode side connected to a voltage wiring 10-6 of a voltage power source VD.
The reference numeral 10-7 denotes an MOS type field effect transistor for pixel selection which has a drain electrode connected to a source electrode of the MOS type field effect transistor 10-5 for amplification and has a source electrode connected to a signal output wiring 10-8.
The signal output wiring 10-8 is grounded at an output terminal through a load circuit 10-9 and serves to output a signal voltage depending on a voltage (VPIX) of the N side electrode 10-3 of the photodiode 10-1 through a source follower circuit which is equivalently constituted by the MOS type field effect transistor 10-5 for amplification and the load circuit 10-9.
Next, the operation of the pixel shown in FIG. 5 will be described.
FIGS. 6A, 6B and 6C are timing charts illustrating the operation of a conventional pixel.
In FIGS. 6A, 6B and 6C, ΦRS denotes a pulse to be input to the gate electrode of the MOS type field effect transistor 10-2 for reset.
Moreover, ΦRD denotes a pulse to be input to the gate electrode of the MOS type field effect transistor 10-7 for pixel selection.
Furthermore, VPIX denotes a change in the electric potential of the N side electrode 10-3 of the photodiode 10-1.
First of all, ΦRS is set to H at a time t0, and the electric potential VPIX of the N side electrode 10-3 of the photodiode 10-2 is set to have a reset voltage VRS.
Next, the MOS transistor 10-2 for reset is turned off at t1, and the N side electrode 10-3 of the photodiode is brought into a floating state.
When light is incident on the pixel, an optical generating current flows to the photodiode 10-1 and electric charges of an electron optically generated are accumulated in the N side electrode 10-3 of the photodiode 10-1. Consequently, the electric potential VPIX is gradually dropped.
Next, when the MOS type field effect transistor 10-7 for pixel selection is turned on at a time t2, a voltage output corresponding to the electric potential VPIX of the N side electrode 10-3 of the photodiode 10-1 at the time t2 is output to the signal output wiring 10-8.
The VPIX depends on the amount of electric charges accumulated in the N side electrode 10-3 of the photodiode 10-1. Therefore, the output of the signal output wiring 10-8 is monitored so that the amount of the accumulated electric charges is estimated. After all, the amount of the incident light can be detected.
In the case in which each pixel has a signal amplifying function, it is necessary to consider that the picture quality of an output image should be prevented from being remarkably deteriorated due to noises generated on an output due to an offset variation.
Such a noise is fixed to a pixel position and is referred to as a fixed pattern noise (hereinafter referred to as “FPN”).
For example, Jpn. Pat. Appln. KOKAI Publication No. 56-46374 has disclosed a general method of suppressing the generation of the FPN.
Moreover, Jpn. Pat. Appln. KOKAI Publication No. 08-004127 has disclosed an example of suppressing the generation of the FPN which is applied to an amplification type imaging element.
An FPN canceling method will be described below.
FIG. 7 simply shows the structure of an image device comprising a reading circuit for canceling the FPN.
In FIG. 7, the reference numeral 12-1 denotes a pixel array section constituted by a plurality of pixels 12-2 arranged two-dimensionally, for example, in a matrix.
Moreover, the reference numeral 12-3 denotes a vertical scanning circuit for selecting the row of the pixel array section 12-2.
Furthermore, the reference numeral 12-4 denotes a horizontal scanning circuit for selecting the output column of the pixel array section 12-2.
A selecting pulse input terminals and a reset pulse input terminals of the pixels in a row are connected to a row selecting line 12-5 and a row reset line 12-6 respectively, and are controlled with a scanning signal output from the vertical scanning circuit 12-3.
Moreover, the signal output terminals of the pixels in a column are connected to a signal output line 12-7, and a signal output to the signal output line 12-7 is input to an FPN canceling section 12-18 provided in column parallel.
The FPN canceling circuit 12-18 is constituted by two sample hold circuits including a switch 12-9, a capacitor 12-11, and a switch 12-10 and a capacitor 12-12.
The capacitor 12-11 is connected to a first video signal line 12-15 through a horizontal selecting switch 12-13, and the capacitor 12-12 is connected to a second video signal line 12-16 through a horizontal selecting switch 12-14.
These first video output line 12-15 and the second video output line 12-16 are connected to the positive and negative input terminals of a differential amplifier 12-17, respectively.
The differential amplifier 12-17 outputs a difference between signals input to the positive input terminal and the negative input terminal, respectively.
FIGS. 8A to 8E are timing charts illustrating the operation the imaging device comprising the FPN cancel reading circuit constituted as described above.
Next, an FPN canceling operation will be described based on a chart timing shown in FIGS. 8A to 8E.
First of all, a row selecting pulse ΦRD-I (i) is output from the vertical scanning circuit 12-3, and a pixels in a first row is selected simultaneously at a time t0 for a horizontal blanking period.
Next, a sample hold pulse ΦSH1 is set to H and the output voltage of the pixel 12-1 obtained after photoelectric charge accumulation is stored in the capacitor 12-11 at a time t1.
Then, after the pixel 12-1 is reset at a time t2, a sample hold pulse ΦSH2 is set to H at a time t3 and an output obtained after pixel resetting, that is, an offset output voltage is stored in the capacitor 12-12.
Thereafter, a horizontal selecting pulse ΦH-J is output from the horizontal scanning circuit 12-4, a signal stored in the capacitor 12-11 is output to the first video signal line 12-15 through the horizontal selecting switch 12-13 and the horizontal selecting switch 12-14 and a signal stored in the capacitor 12-12 is output to the second video signal line 12-16 for a horizontal scanning period.
The differential amplifier 12-17 outputs a difference between signals input from the first video signal line 12-15 and the second video signal line 12-16 to the positive input terminal and the negative input terminal, respectively.
With such a structure, it is possible to suppress the FPN caused by a variation in the characteristics of the pixel and the selecting switch.
However, also in the solid state imaging device having the FPN improved for reading, there is a further problem in that random noises remain.
As a main cause of the random noise, thermal noises made by resetting the photodiode section of the pixel have the greatest influence.
More specifically, in FIG. 5, when the photodiode 10-1 is to be reset, the voltage of the N side electrode 10-3 of the photodiode 10-1 fluctuates at the moment that the MOS type field effect transistor 10-2 for reset is turned off.
The N side electrode 10-3 of the photodiode 10-1 is connected to the gate electrode of the MOS type field effect transistor 10-5 for amplification to be used for reading. Therefore, when the voltage of the gate electrode of the field effect MOS transistor 10-5 for amplification to be used for reading fluctuates, there is a problem in that an offset fluctuation is generated on an output and the picture quality of an output image is remarkably deteriorated.
The voltage fluctuation of the N side electrode 10-3 of the photodiode 10-1 has a standard deviation of (kT/C)1/2.
k represents a Boltzmann's constant, T represents an absolute temperature and C represents a total capacitance for a ground present equivalently to the N side electrode 10-3 of the photodiode 10-1.
The voltage fluctuation is randomly generated for each reset operation. Therefore, a difference between two-time reset operations shown in FIGS. 7 and 8A to 8E is taken so that 21/2 multiplication is carried out in the operation for suppressing the FPN and a noise of (2kT/C)1/2 is actually mixed into a video output.
In general, this noise is referred to as a reset noise or a kTC noise.
In a conventional amplification type CMOS pixel, there has been a problem in that a high sensitivity cannot be obtained due to the reset noise made by resetting the photodiode and the same CMOS pixel is not suitable for the use of high picture quality.
For example, in the case in which a pixel has a value C of 10 fF, a value of the reset noise at a room temperature is represented as approximately 60e− in an equivalent input charge number which is several times as large as an ordinary CCD noise. Consequently, there is a problem in that the high picture quality cannot be obtained.
In order to suppress the reset noise or to perform improvement so as not to generate the reset noise, for example, it can also be proposed that the photodiode section of the pixel is constituted by a CCD element and an electric charge is completely transferred as in the CCD such that no electric charge is present in an electric charge accumulating section after resetting.
However, in the case in which the photodiode is to be implemented with a CCD structure, it is necessary to employ a structure in which the gate electrode of an MOS capacitor constituting the photodiode is made transparent such that light can be incident thereon and a transfer gate is provided. This is greatly different from a general-purpose CMOS process. Therefore, there is a problem in that a feature such as original manufacturing easiness is lost.
In a conventional technique, a method of suppressing a reset noise without greatly departing from the general-purpose CMOS process has not been proposed.
Conventionally, there has been proposed and practically utilized a signal charge detecting device to be used for the solid state imaging element in which a change in an input voltage signal is injected as a signal charge to a circuit through a capacitor and the change amount of an input voltage is calculated by using the injected signal charge.
In a CMOS circuit which has been remarkably advanced, recently, it is easy to constitute a capacitor element in a semiconductor process. Therefore, an analog circuit applying a capacitor element has actively been developed and utilized.
As an example, Jpn. Pat. Appln. KOKAI Publication No. 57-202118 has disclosed a comparator circuit constituted to inject an electric charge to an MOS inverter circuit through a capacitor element and a method of relieving the noise of the comparator circuit.
As a further application example, Jpn. Pat. Appln. KOKAI Publication No. 58-104524 has disclosed a method of constituting ADC by using the comparator circuit.
In the prior art, however, there has been a problem in that great thermal noises are made when the electric charges accumulated in the capacitor element for input are to be initialized (reset). In order to solve the problem, it is necessary to increase the size of the capacitor element for input.
Consequently, the input capacitor of the circuit is increased. As a result, there is a problem in that great power consumption is required for driving and the area is hard to reduce when the circuit is to be integrated on a chip.
By taking, as an example, the comparator circuit used in the conventional art, the above-mentioned problems will be explained for clearer designation.
FIG. 11 shows the structure of a conventional typical charge detecting device.
As shown in FIG. 11, a charge input terminal 101 is connected to a ground potential point through a capacitor C1 and is connected to the negative input terminal (−) of a differential amplifier circuit (amplifier circuit) 130.
The negative input terminal (−) of the amplifier circuit 130, that is, the charge input terminal 101 and the output terminal of the amplifier circuit 130 are connected to each other through a reset switch 104.
A first reset pulse RS1 is applied to a control terminal 114 of the reset switch 104.
A reference voltage VREF is input to the positive electrode (+) side of the amplifier circuit 130.
Even if the amplifier circuit 130 is replaced with an inverter circuit disclosed in the above-mentioned prior art, that is, Jpn. Pat. Appln. KOKAI Publication No. 57-202118 and Jpn. Pat. Appln. KOKAI Publication No. 58-104524, the basic operation is identical.
Next, the operation of the conventional charge detecting device shown in FIG. 11 will be described based on a timing chart shown in FIGS. 12A and 12B.
FIGS. 12A and 12B show a reset pulse RS1 applied to a control terminal 114 of the reset switch 104 and an electric potential VIN of the charge input terminal 101 in time series along an operation sequence.
For simplicity of explanation, the reset switch 104 is closed when the reset pulse RS1 has a positive logic.
First of all, the electric potential VIN of the charge input terminal 101 is optional in the initial state before a time t1.
When the reset pulse ΦRS1 is input at the time t1 and the reset switch 104 is closed, the output terminal and the negative input terminal (−) of the amplifier circuit 130 are short-circuited. Therefore, the amplifier circuit 130 operates as an analog buffer circuit.
Consequently, the electric potential VIN of the charge input terminal 101 is set to a reference voltage VREF through a finite ramping period.
Next, when the ΦRS1 is changed to open the reset switch 104 at a time t2, the charge input terminal 101 is brought into a floating state on a DC basis so that electric charges can be accumulated.
Then, signal charges are injected into the charge input terminal 101. Consequently, if the injected charge is positive, a negative potential is output to the output terminal of the amplifier circuit 130. If the injected charge is negative, a positive potential is output to the output terminal of the amplifier circuit 130.
More specifically, the present charge detecting device serves to operate as a charge detecting comparator for a negative output.
The conventional charge detecting device shown in FIG. 11 generates a thermal noise ΔVIN made with the switching operation of the reset switch 104.
The thermal noise ΔVIN is generated for the ground capacitor value of the charge input terminal 101 and a noise voltage expressed in Equation (1) is generated as a mean noise.ΔVIN(t=t2)=SQRT(kT/C1)  (1)
wherein k represents a Boltzmann's multiplier and T represents an absolute temperature.
The noise voltage is randomly generated. As a result, the noise detecting limit of the electric detecting device is determined so that detection precision is deteriorated.
Furthermore, at the moment that the reset switch 104 is closed, a parasitic capacitor component present between the control terminal 114 of the reset switch 104 and the charge input terminal 101 and an electric charge forming the channel of the reset switch 104 are pushed out toward the charge input terminal 101 through a reset operation.
This is referred to as a feed through phenomenon. If the same phenomenon is present, an offset charge is equivalently generated. Consequently, there is a problem in that the initial potential of the charge input terminal 101 during resetting is shifted from a balancing point for a comparator.